As a non-volatile semiconductor memory, such as an electrically erasable and programmable read only memory (EEPROM) device, there is disclosed in Japanese Patent Kokai Publication JP-A-5-174583, an X-cell configuration of a split-gate type non-volatile semiconductor memory device that enabled a high integration being substantially the same as with stack-gate type memory cells. In this split-gate type non-volatile semiconductor memory device, each memory cell has an address gate electrode and a memory gate electrode. Referring to FIGS. 16 and 17, the non-volatile semiconductor memory device described in the above-mentioned Japanese Patent Kokai Publication JP-A-5-174583 will be described. Since the device has a layout configuration in which four memory cells 310, 320, 330, and 340 share one contact region 360 and are disposed in an X pattern with the region 360 being a center, the configuration is referred to an X-structure layout or an X-cell. Incidentally, the X-cell will also be referenced from Japanese Patent Kokai Publication JP-A-5-343645, for example.
Referring to a partial circuit diagram shown in FIG. 16, there are arranged four memory cells 310, 320, 330, and 340. The memory cells 310 and 340 constitute part of memory cells of a row connecting an upper left and a lower right of the drawing, while the memory cells 320 and 330 constitute part of memory cells of a row connecting an upper right and a lower left of the drawing. In addition, three are provided bit lines Bi−1, Bi, and Bi+1, extending in parallel from top to bottom.
The bit line Bi is connected to one of source/drain electrodes 311 and 312, 321 and 322 and 331 and 332, and 341 and 342, or the electrodes 312, 322, 331, and 341, via a bit contact 360.
The bit line Bi−1 is connected to the other one of the source/drain electrodes 311 and 332 of the memory cells 310 and 330 via bit contacts 361 and 362, respectively.
The bit line Bi+1 is connected to the other one of the source/drain electrodes 321 and 342 of the memory cells 320 and 340 via bit contacts 363 and 364, respectively.
Each memory cell is comprised of two transistors: address selection transistors and memory transistors (devices encircled in FIG. 16).
A memory transistor of the memory cell 310 having a memory gate electrode 314 is connected to the bit line Bi−1 via the bit contact 361.
The memory transistors of the memory cells 320 and 330 having memory gate electrodes 324 and 334 respectively are connected to the bit line Bi via the bit contact 360.
The memory transistor of the memory cell 340 having a memory gate electrode 344 is connected to the bit line Bi+1 via the bit contact 364.
The memory gate electrode 314 of the memory transistor in the memory cell 310 and the memory cell electrode 324 of the memory transistor in the memory cell 320 are composed by a word line W1, while address gate electrodes 313 and 323 of their address selection transistors are composed by an address gate line X1.
The memory gate electrode 334 of the memory transistor in the memory cell 330 and the memory gate electrode 344 of the memory transistor in the memory cell 340 are composed by a word line W2, while the address gate electrodes 333 and 343 of their address selection transistors are composed by an address gate line X2.
FIG. 17 is a layout diagram of a circuit shown in FIG. 16 on a semiconductor chip. The address gate line X1 and the word line W1 cross to each other. Likewise, the address gate line X2 and the word line W2 also cross to each other.
The above mentioned layout is adopted for the sake of the operations of programming and erasing memory the transistors.
An operation of programming the memory cell 320 will be described by way of an example. 9V is applied to the word line W1 of the memory cell 320. 0V voltage is applied to the bit line Bi, while 9V is applied to the bit line Bi−1. At this point, 0V is applied to the address gate line X1. Programming (which is termed as “Fowler-Nordheim tunneling”, or also termed as “F-N tunneling”) the memory cell 320 is thereby performed.
At this point, 0V are applied to both of the address gate line X2 and the word line W2 for the memory cells 330 and 340, so that the F-N tunneling does not occur. Thus, no programming is performed.
Furthermore, since the word line W1, address gate line X1, and bit line Bi for the memory cell 310 are the same as in the memory cell 320 and a program inhibiting voltage of 9V is applied to the bit line Bi−1. Thus, programming the memory cell 310 is not performed.
The reason why the address gate line X1 and the word line W1 cross to each other is to prevent occurrence of erroneous programming the memory cell 310 when the writing operation to the memory cell 320 is performed. That is, when the programming the memory cell 320 is performed, arrangement is made so that the program inhibiting voltage of 9V can be applied to the memory transistor of the memory cell 310 from the bit line Bi−1.
The reason why one memory cell is constituted from two transistors, or has a split-gate configuration including the address gate electrode and the memory gate electrode is that if programming caused by the F-N tunneling is employed for an X cell, an adjacent cell is also programmed simultaneously. This problem will be described with reference to FIG. 18 that schematically shows two adjacent memory cells. Referring to FIG. 18, reference numeral 1 denotes a P-type semiconductor substrate, reference numerals 2A, 2B, and 2C denote N+ diffusion regions, reference numerals 3A and 3B are ONO films each constituted from a silicon oxide film, a silicon nitride film, and the silicon oxide film, and reference numerals 4A and 4B denote gate electrodes. A first memory cell is composed by the diffusion regions 2A and 2C, ONO film (of the silicon oxide film, silicon nitride film, and silicon oxide film) 3A, and gate electrode 4A. A second memory cell is composed by the diffusion regions 2B and 2C, ONO film 3B, and gate electrode 4B. The word line for the first and second memory cells is commonly connected. By applying a high voltage to the gate electrodes 4A and 4B through the word line and a ground potential (0V) is applied to a contact for the diffusion region 2C, the second memory cell adjacent to the first memory cell is also programmed simultaneously. For this reason, as shown in FIGS. 16 and 17, the memory cell is composed by two transistors including the address selection transistor and the memory transistor.
In a configuration described with reference to FIGS. 16 and 17, since one memory cell is constituted from two elements of the address selection transistor and the memory transistor, memory cell size increases.
Further, in the configuration described with reference to FIGS. 16 and 17, a structure where the address gate line and the word line cross to each other is essential for applying a program inhibit voltage to a memory cell not to be programmed so as to prevent occurrence of multiple simultaneous programming of the memory cell not to be programmed. This structure is difficult to be manufactured in view of process technology.
In addition, in the configuration described with reference to FIGS. 16 and 17, there are overlaps between the address gate line and the word line. Thus, application of a silicidation/salicidation process, which is commonly employed in a manufacturing process of a logic device is difficult.
A configuration disclosed in U.S. Pat. No. 6,256,231 B1 as other related art will be described. As shown in FIG. 19, in one memory cell transistor, there is provided nodes 26 and 28 for storing two bits information to achieve high integration of memory cells. Referring to FIG. 19, reference numeral 12 denotes the P-type silicon substrate, reference numeral 14 denotes a source diffusion region, reference numeral 16 denotes a drain diffusion region, reference numerals 18, 20, and 22 denote the silicon oxide film, silicon nitride film, and the silicon oxide film, respectively, which constitute the ONO film, and reference numeral 24 denotes the gate electrode. In a memory cell array configuration, as shown in FIG. 20, buried N-type diffusion regions 1101, 1102, and 1103 are formed in a P-type silicon substrate 1110 to be employed as bit lines. Further, silicon oxide films 1124 are formed over the N-type diffusion regions 1101, 1102, and 1103. Between the mutually adjacent N-type diffusion regions such as between the N-type diffusion regions 1101 and 1102, N-type diffusion regions 1102 and 1103, N-type diffusion region 1103 and an adjacent diffusion region not shown, ONO films 1111, 1112, and 1113 are formed respectively to function to trap electrons injected into a memory cell.
Over the silicon oxide films 1124 and the ONO films 1111 to 1113, word lines made of impurity-doped polycrystalline silicon (termed as “polysilicon”) 1126 and metal silicide 1127 are formed.
However, the configuration shown in FIG. 20, is such a structure to which the application of a salicide process employing commonly used a refractory metal (which has a high melting point) such as W, Mo, Ta, Ti, or the like or a semi-precious metal such as Co is extremely difficult.
More specifically, the silicon oxide films 1124 formed over the N-type diffusion regions and the ONO films 1111 to 1113 formed on the silicon substrate have a film thickness which is comparatively thin. On the other hand, as will be described later, before formation of a metal silicide layer using a refractory metal, a sidewall spacer is formed. The side wall spacer is formed because of a need for providing electrical insulation so that a short circuit between the gate electrode and the N-type diffusion region may not occur due to the metal silicide layer.
For the formation of the sidewall spacer, generally, the silicon oxide film is deposited over the substrate by CVD (Chemical Vapor Deposition) or the like, and then an etch back process using dry etching such as RIE (Reactive Ion Etching) is performed. During a step of this etch back process, the comparatively thin ONO films 1111 to 1113 and the silicon oxide films 1124 are removed by etching and hence the N-type diffusion regions and the silicon substrate 1110 are exposed.
In this state, an electrical short circuit occurs between the N-type diffusion region and the silicon substrate due to the refractory metal, deposited on an entire surface of the substrate. An operational failure is thereby caused. In the memory cell array configuration shown in FIG. 20, the silicidation is extremely difficult.
As a single-transistor EEPROM with an ONO gate insulating film, using single polysilicon, where programming is performed by hot electron injection, the description in such a reference as “A True Single-Transistor Oxide-Nitride-Oxide EEPROM device”, IEEE EDL-8, No. 3, 1987, P.93 by T. Y. CHAN et al. can also be referred.